1. Field of the Invention
The invention relates to a semiconductor device and, more particularly, to a semiconductor device with substrate-triggered electrostatic discharge (ESD) protection.
2. Description of the Related Art
The electrostatic protection is one of the important issues of the integrated circuits. Since the electrostatic charge is accompanied with a relatively high voltage (may be several thousands volts), those skilled in the art may utilize an electrostatic discharge (ESD) protection circuit to protect the semiconductor device, thereby preventing the semiconductor device from being damaged by the electrostatic charge.
Referring to FIG. 1A, a conventional semiconductor device 1 with ESD protection includes a guard ring 11 and a MOS (Metal-Oxide-Semiconductor) transistor array 12. The MOS transistor array 12 has a plurality of MOS transistors, each of which is composed of a source 121, a drain 122 and a gate 123. The circuit layout of the gate 123 is of a finger-type. As shown in FIG. 1B, a plurality of N+ diffusion areas and a plurality of P+ diffusion areas are formed on a substrate 20. The N+ diffusion areas 21 and 22 serve as the source 121 and the drain 122 shown in FIG. 1A, respectively. The P+ diffusion area 23 serves as the guard ring 11 shown in FIG. 1A. The N+ diffusion areas 21 and 22 and the substrate 20 form a parasitic bipolar junction transistor (parasitic BJT) 24. Thus, the junction between the base and the emitter of the parasitic BJT 24 is forward biased by the ESD pulse, such as of a human-body mode (HBM), in order to trigger the parasitic BJT 24 into an active region. Thus, the MOS transistor array 12 can be protected.
However, the finger-type NMOS transistors as described above cannot be uniformly triggered as expected, but only a part of the fingers are activated. The result is that the semiconductor device 1 is easily subjected to ESD damage. Therefore, even if there are more MOS fingers forming the parasitic BJT in the semiconductor device 1 to discharge the electrostatic charge, the ESD robustness of the semiconductor device 1 is still very low. In other words, since the turn-on speeds of the fingers are different from one another, the turn-on uniformity is not good. Thus, the ESD protection level of the semiconductor device does not come up to expectation.
In order to overcome the aforementioned problem, those skilled in the art may improve the turn-on uniformity of each finger by various circuit tricks. One of the most commonly used methods is to use a substrate-triggered ESD protection circuit for improving the turn-on uniformity of the MOS fingers. Referring to FIG. 2A, a conventional semiconductor device 3 with substrate-triggered ESD technique includes a guard ring 31 and a MOS transistor array 32. The MOS transistor array 32 has a plurality of MOS transistors 321, a plurality of fingers 322 constituted by the gates of the MOS transistors 321, and a plurality of substrate-triggered areas 323 between the fingers 322. As shown in FIG. 2B, a plurality of N+ diffusion areas and a plurality of P+ diffusion areas are formed on a substrate 40. Since the diffusion areas are similar to those of the aforementioned semiconductor device 1, detailed description thereof is omitted. The semiconductor device 3 is different from the aforementioned semiconductor device 1 in having a plurality of P+ diffusion areas 41 and a plurality of isolation portions 42. Each of the isolation portions 42 can be a shallow trench isolation (STI) portion for separating the P+ diffusion areas 41 from the N+ diffusion areas. Thus, when the ESD event occurs, the trigger current Itrig flows through the P+ diffusion areas 41 to the substrate 40, and then the bases of parasitic BJTs 43 and 44 are biased. Accordingly, the parasitic BJTs 43 and 44 can be triggered simultaneously to discharge the electrostatic charge. Therefore, the turn-on uniformity of each finger can be efficiently improved.
To sum up, the turn-on uniformity of each finger can be efficiently improved by forming a substrate-triggered area between two adjacent fingers. However, since three substrate-triggered areas 323 (as shown in FIG. 2A) have to be provided for four fingers 322, these substrate-triggered areas may increase the area of the circuit layout. In other words, in each MOS transistor array, there is a large area not formed with MOS transistors. Therefore, the number of the MOS transistors in the MOS transistor array greatly decreases due to the provision of the substrate-triggered area. The manufacturing cost of the semiconductor device is thus increased.
As above, it is an important subject matter to provide the substrate-triggered area so as to improve the ESD protection ability of the semiconductor device without greatly increasing the area of the circuit layout.
In view of the aforementioned problem, it is an important object of the invention to provide a semiconductor device with substrate-triggered ESD protection technique and having a substrate-triggered area capable of improving the ESD protection ability without greatly increasing the area of the circuit layout.
To achieve this object, a semiconductor device with substrate-triggered ESD protection in accordance with one aspect of the invention includes a guard ring, a first MOS transistor array, a second MOS transistor array and a substrate-triggered portion. In the invention, the first MOS transistor array, the second MOS transistor array and the substrate-triggered portion are formed in a region surrounded by the guard ring, and the substrate-triggered portion is located between the first MOS transistor array and the second MOS transistor array. The first MOS transistor array has at least one first finger-type gate extending in a first direction. Also, the second MOS transistor array has at least one second finger-type gate extending in the first direction. The substrate-triggered portion is arranged to extend in a second direction perpendicular to the first direction. When an ESD event occurs, the substrate-triggered portion can pass a trigger current to bias a base of at least one parasitic BJT in the first MOS transistor array and a base of at least one parasitic BJT in the second MOS transistor array. As stated above, an isolation portion is further formed among the guard ring, the first MOS transistor array, the second MOS transistor array and the substrate-triggered portion.
In addition, in another aspect of the invention, the semiconductor device with substrate-triggered ESD protection further includes a first N-well and a second N-well. The first N-well and the second N-well are formed between the first MOS transistor array and the second MOS transistor array, and located near two ends of the substrate-triggered portion, respectively.
To sum up, in the semiconductor device with substrate-triggered ESD protection design in accordance with the invention, the substrate-triggered portion is formed between two MOS transistor arrays, but not formed between two fingers in one MOS transistor array. As a result, it can be used for improving the ESD protection ability of the semiconductor device without greatly increasing the area of the circuit layout with this design.